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The present invention provides a system and method for fabricating high reliability capacitors, inductors, and multi-layer interconnects on hybrid microelectronic substrate surfaces using thin film technology. Specifically, it employs a thin lower electrode layer under a patterned dielectric layer. Conventional thin film conductors, upper electrodes for capacitors, spiral inductors, and resistor elements are then deposited on top of the dielectric layer to form thin film hybrid microelectronic devices containing conductors, capacitors, inductors, and resistors all integrated together on the same device.
Hybrid microelectronic devices are manufactured on a variety of substrate materials using various techniques such as thick film, low temperature co-fired ceramic (LTCC), specialty printed circuit board (PCB), or thin film technology. Hybrid devices are used in many microelectronics applications in the defense, medical, communications, computer, automotive, and infrared imaging industries, as well as in many other applications. In all of these industries there is continuous demand for devices that offer improved performance and function. In order to satisfy these demands, the number of passive devices (capacitors, inductors, and resistors) designed into microelectronic devices continues to grow. For instance, a typical cellular phone product may contain 400 components with less than 20 devices being active (i.e., semiconductors) and the 380 or more devices being passive devices.
Along with demands for better performance are also requirements to provide products that are less expensive and smaller in size. It is reported that the passive components in a cellular phone product can occupy 80% of the printed circuit board area and account for 70% of the product assembly costs. Thus, there is clear need to reduce the size and cost of the passive devices required in microelectronic devices.
Of the hybrid circuit fabrication techniques, thin film technology is extremely well suited for use in RF/microwave, wireless, and optical transmission technologies because of its ability to provide high quality features, extremely dense packaging, and a large range of integrated features.
The current state of the art in thin film hybrid microelectronic manufacturing offers cost effective, high reliability methods for integrating conductors, inductors, and resistors onto the same thin film hybrid circuit device but not capacitors and interconnects (i.e. connections between devices and multiple layers).
Presently, capacitors are typically purchased individually and attached to the thin film devices using various surface mount die attach techniques. The individual chip capacitors take up valuable space, require much assembly labor, and can decrease reliability due to assembly problems.
Interconnects are often required to interconnect components and devices and to attach to the center of spiral inductors and power splitters such as Lange couplers. Current technology uses wire or ribbon bonding to make individual interconnects. Wire or ribbon bonds can add higher costs and sometimes cause high frequency performance problems due to bond inconsistencies, different bond shapes or the bonds falling over and shorting to conductor lines that they are crossing over.
Thus, there is a clear need for a reliable fabrication method that offers both integrated capacitors and integrated interconnects. It is especially desirable that this method provides features that are usable from DC to very high operating frequencies. The prior art does not satisfy this need.
A recent approach to the integration of capacitors and interconnects has concentrated on fabricating these devices on silicon wafers. See MARC DE SAMBER, NICK PULSFORD, MARC VAN DELDEN, ROBERT MILSOM; xe2x80x9cLow-Complexity MCM-D Technology with Integrated Passives for High Frequency Applicationsxe2x80x9d, The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 2, Second Quarter 1998, pgs 224-229 (ISSN 1063-1674) (International Microelectronics and Packaging Society).
This paper presented simple concepts for fabricating integrated capacitors, inductors, resistors, and interconnects on silicon wafers. However, processing thin film hybrid substrates offers unique challenges when compared to silicon wafers, and the teachings presented in this prior art are not directly applicable to thin film hybrid substrate processing.
Two basic techniques have been used in the past to fabricate integrated capacitors onto thin film hybrid devices. Both techniques are based on the xe2x80x9cparallel platexe2x80x9d construction or MIM (metal-insulator-metal) capacitor design. Both techniques are inherently difficult to manufacture as they need to address the issue of xe2x80x9cstep coveragexe2x80x9d of the dielectric layer over the thick bottom electrode.
FIG. 1 (0100) illustrates a MIM technique whereby a thin lower electrode (0102) is deposited and patterned on a substrate (0101). This lower electrode (0102) is then oxidized or anodized to form a thin oxide layer (0103) on its top surface that then becomes the dielectric layer in the capacitor. An upper electrode layer (0104) is then deposited and patterned on top of the insulator layer (0101) to form a MIM capacitor.
This type of capacitor is very difficult to manufacture as it presents many problems such as capacitance value reproducibility problems, shorting (0106) of the top electrode (0104) to the bottom electrode (0102) through the thin dielectric (0105), low breakdown voltage, low Q (quality factor) at high frequencies, and wire bonding challenges.
The capacitor value or capacitance is inversely proportional to the thickness of the dielectric layer so it is very advantageous to have the dielectric layer as thin as possible. When depositing a thin dielectric layer over a thicker electrode layer electrical shorts are introduced at the edge (0106) of the bottom electrode (0102) due to poor xe2x80x9cstep coveragexe2x80x9d (0105) of the dielectric layer (0103) as shown in FIG. 1 (0100).
FIG. 2 (0200) illustrates a MIM technique that uses a thick bottom electrode (0202), a dielectric layer (0203), and air-bridges (0204, 0205, 0206) to crossover to the upper electrode layer (0207). This technique uses multiple deposition and patterning processes to build up and then cross over to the upper electrode layer (0207).
This process is inherently difficult because the lower electrode (0202) is relatively thick, thereby making it problematic to make contact to the upper electrode (0207) without shorting to the thick lower electrode (0202). Most dielectric coatings (0203), in order to be applied at a thickness that will completely cover the lower electrode layer (0202), exhibit extremely low capacitance densities and therefore are used only rarely. Therefore, the air-bridge method becomes a logical method for making a connection to the upper electrode (0207) because it can use thinner dielectrics with higher capacitance densities.
This method exhibits manufacturing and repeatability problems due to its very complex nature. It is extremely expensive and problematic to produce. It also suffers from reliability problems because the air bridges are vulnerable to shorts from handling.
In an effort to fabricate integrated interconnects, a xe2x80x9ccrossoverxe2x80x9d or xe2x80x9cair-bridgexe2x80x9d technique has also been employed, as described in FIG. 3 (0300). This technique uses multiple deposition and patterning processes on a substrate (0301) to build up (0303) and then crossover (0304) thick conductor traces (0302) to form interconnects. The processes are typically expensive and therefore can usually only be used in high volume production or in specialty applications that are not cost sensitive. Additionally, the air-bridge spans (0304) are fragile and can be deformed or collapsed by simple handling. It is also important to note that due to the complex nature of the air-bridge process, it is extremely rare for air-bridge interconnects and air-bridge capacitors to be produced on the same device.
A more complex version of the simple air-bridge is to support the crossover span (0402) with an underlying insulating material (0403), as illustrated in FIG. 4 (0400). Supported crossovers prevent the cross over span from being deformed and causing it to short to the conductor lines underneath. Usually polyimide is used as the supporting insulation.
The addition of the insulating support (0403) under the span (0402) increases the complexity and cost of the supported crossover process. It is again important to note that due to the complex nature of the supported air-bridge process, it is extremely rare for supported air-bridge interconnects and air-bridge capacitors to be produced on the same device.
The prior art in this area relates generally to the following U.S. Pat. Nos.: 3,969,197; 4,002,542; 4,002,545; 4,038,167; 4,062,749; 4,364,099; 4,408,254; 4,410,867; 4,423,087; 4,471,405; 4,599,678; 4,631,633; 5,122,923; 5,258,886; 5,262,920; 5,338,950; 5,390,072; 5,455,064; 5,539,613; 5,587,870; 5,643,804; 5,670,408; 5,685,968; 5,693,595; 5,699,224; 5,708,302; 5,736,448; 5,737,179; 5,745,335; 5,760,432; 5,767,564; 5,781,081; 5,818,079; 5,872,040; 5,874,379; 5,877,533; 5,882,946; 5,883,781; 5,889,299; 5,907,470; 5,912,044; 5,936,831; 5,943,547; 5,973,908; 5,973,911; 5,982,018; 6,001,702; 6,023,407; 6,023,408; 6,040,594; 6,069,388; 6,072,205; 6,075,691.
These patents generally address the following general areas:
1. Fabrication of capacitors on silicon wafers. Unfortunately, the manufacturing techniques utilized here are inapplicable to thin film hybrid substrate fabrication.
2. Fabrication of capacitors on thick film hybrid substrates. While these techniques do permit capacitor fabrication, the performance of these devices is limited and their manufacturing yield is generally low due to step coverage problems and/or problems with crossover bridge spans.
3. Fabrication of capacitors on thick film hybrid substrates using exotic plating techniques. These systems generally have high manufacturing costs and lower device performance than the present invention.
None of the prior art teaches the use of very thin metalization for the bottom plating of capacitors to avoid step coverage problems and improve manufacturing yield.
The present invention provides a system and method for fabricating cost effective, high reliability capacitors and multi-layer interconnects in order to provide the ability to integrate capacitors and interconnects along with conductors, inductors, and resistors all on the same thin film hybrid microelectronic device. Accordingly, the objectives of the present invention are (among others) to circumvent the deficiencies in the prior art and affect one or more of the following:
1. It is an object of this present invention to provide a method for forming capacitors and interconnects on thin film hybrid microelectronic substrates. This method first employs a thin metal layer deposited and patterned on the substrate. This thin patterned layer is used to provide both lower electrodes for capacitor structures and interconnects between upper electrode components. Next, a dielectric layer is deposited over the thin patterned layer and the dielectric layer is patterned to open contact holes to the lower electrode layer. The upper electrode layers are then deposited and patterned on top of the dielectric layer to define the conductors, resistors, and inductors. Thus, by first depositing and patterning the thin lower electrode layer that becomes encapsulated by a suitable dielectric layer under the thick upper electrodes, this invention simply and economically solves many of the problems associated with past methodologies.
2. According to a further object of the present invention, the lower electrode and interconnect layer are made of a material that is mainly gold (Au).
3. According to a further object of the present invention, the lower electrode and interconnect layer are made of a material that is mainly copper (Cu).
4. According to a further object of the present invention, the lower electrode and interconnect layer are made of a material that is mainly silver (Ag).
5. According to a further object of the present invention, the lower electrode and interconnect layer are made of a material that is mainly aluminum (Al).
6. According to a further object of the present invention, the lower electrode and interconnect layer are made of one or more metals selected from a group consisting of tantalum (Ta), tungsten (W), titanium (Ti), nickel (Ni), molybdenum (Mo), platinum (Pt), palladium (Pd), or chromium (Cr).
7. According to a further object of the present invention, the dielectric layer is made of a material that is mainly silicon nitride (Si3N4).
8. According to a further object of the present invention, the dielectric layer is made of a material that is mainly silicon dioxide (SiO2).
9. According to a further object of the present invention, the dielectric layer is made of a material that is mainly silicon oxynitride (SiOxNx).
10. According to a further object of the present invention, the dielectric layer is made of a material that is mainly aluminum oxide (Al2O3).
11. According to a further object of the present invention, the dielectric layer is made of a material that is mainly tantalum pentoxide (Ta2O5).
12. According to a further object of the present invention, the dielectric layer is made of a material that consists of a ferroelectric material that is mainly BaTiO3, SrTiO3, BaTiO3, PbZrO3, PbTiO3, LiNbO3, or Bi14Ti3O12.
13. According to a further object of the present invention, the dielectric layer is made of a material that is mainly polyimide or benzocyclobutene.
14. According to a further object of the present invention, the substrate material is made of one or more of materials selected from a group consisting of alumina (Al2O3), beryllium oxide (BeO), fused silica (SiO2), aluminum nitride (AlN), sapphire (Al2O3), ferrite, diamond, LTCC, or glass.
While these objectives should not be understood to limit the teachings of the present invention, in general these objectives are achieved by the disclosed invention that is discussed in the following sections.
The invention is related in the general area of generating integrated thin film capacitors and other passive components along with associated interconnect. To date, the industry has been unable to commercially fabricate a viable integrated capacitor in the thin film industry. The system and method described in the figures and the following text discloses such a system that can be fabricated using conventional thin film technologies at substantially reduced costs over methods currently used within the industry.